The present disclosure relates to semiconductor devices.
Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC to DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage signal, and filtering the high frequency input voltage signal to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
LDMOS transistors are used in switching regulators as a result of their performance in terms of a tradeoff between their specific on-resistance (Rdson) and drain-to-source breakdown voltage (BVd—s). On-resistance (Rdson) versus the long-term reliability of device is another performance tradeoff.
Referring to FIG. 1, a conventional LDMOS transistor 300 includes a p-type substrate 302 in which is formed a high-voltage n-type well (HV n-well) 304. In the HV n-well are a source region 310 with an n-doped n+ region 312, a p-doped p+ region 314, and a p-doped p-body diffusion (p-body) 316, a drain region 320 with an n-doped n+ region 322 and a more lightly doped n-type doped drain (NDD) 324, and a gate 330 with a gate oxide 332 and a polysilicon layer 334.
In this conventional LDMOS design, a region 340 in the NDD under the gate 330 that is between the n+ region 312 and the HV n-well 304 experiences the highest electrical field due to the depletion region that is developed to support the high drain voltage potential. Because the region 340 is in the current path during the conduction state, significant engineering effort has been made to minimize this high-resistance region. However, minimizing the high-resistance region further increases the electrical field gradient and can result in a high impact ionization rate. Thus, in a conventional LDMOS design, region 340 is the location where device breakdown happens during the off-state.
When breakdown happens at the region 340, a large quantity of holes and electrons are generated in this region 340. These carriers can easily get trapped in the drain-side gate oxide of the device due to their high energy, and cause intrinsic device characteristic degradation and long-term reliability problem such as FET on-resistance degradation. One technique used to avoid intrinsic breakdown in the power LDMOS device is to include a second device with lower breakdown voltage in parallel with the LDMOS device to clamp the drain voltage of LDMOS device. However, such an approach results in a complex system and higher component count and cost.